1. Field of the Invention
The present invention relates to an output circuit for outputting data and a clock.
2. Description of the Related Art
FIG. 8A shows an output circuit for outputting data and a clock in a prior art. A clock signal CKA is propagated via a plurality of buffers 801. A clock signal CKIN is an output from the buffers 801.
A D-type flip-flop (hereinafter referred to as flip-flop) 803 outputs data DTIN to a selector 805 in synchronization with the clock signal CKIN. The selector 805 selectively outputs either an output from the flip-flop 803 or an output from a BSR (Boundary SCAN register) 804 as output data DTOUT. Although this example is a case of outputting 1-bit output data DTOUT, if plural bits of the output data DTOUT are outputted, plural sets of the flip-flop 803, BSR 804, and selector 805 are connected in parallel.
A delay circuit 810 outputs a clock signal CKOUT by delaying the clock signal CKIN for predetermined time in order to output the data DTOUT and the clock signal CKOUT simultaneously. This delay time needs to be the same as delay time of the flip-flop 803 and the selector 805.
FIG. 8B shows a concrete configuration of the delay circuit 810. The delay circuit 810 is configured by connecting an even number of inverters 821 in series.
FIG. 8C shows another concrete configuration of the delay circuit 810. The delay circuit 810 is configured by connecting an even number of inverters 831 and 833 and a transfer gate 832 in series. The transfer gate 832 is composed of an n-channel MOS (metal-oxide-semiconductor) transistor 832n and a p-channel MOS transistor 832p. A gate of the n-channel MOS transistor 832n is maintained at the high level and a gate of the p-channel MOS transistor 832p is maintained at the low level. Accordingly, the transistors 832n and 832p turn on together and become equal to a delay element composed of their on-resistance and capacity.
When the data and the clock are outputted simultaneously, the flip-flop 803 is provided in a path of the data while a flip-flop is not provided in a path of the clock, in general. Further, the delay circuit 810 having the same delay time as that of the flip-flop 803 and selector 805 needs to be added into the path of the clock.
However, the flip-flop 803 is a circuit system which outputs the data in synchronization with either the rise or the fall of the clock signal CKIN while the delay circuit 810 is composed of the inverters 821 or the transfer gate 832. Therefore, it is difficult to set the delay time of the delay circuit 810 as the same delay time as that of the flip-flop 803 and selector 805.
Moreover, when the clock signal CKA is propagated in a semiconductor, the duty is deteriorated depending on process variations of the semiconductor and the magnitude of a load to be driven in some cases. Particularly, when a CMOS circuit is used, characteristics of a p-channel MOS transistor and an n-channel MOS transistor are different from each other and the deterioration of the duty because of the process variations of the semiconductor cannot be prevented.